1. Field of the Invention
The present invention relates to a layout method, a layout program and a layout system for a semiconductor integrated circuit, and particularly to a layout method, a layout program and a layout system for a semiconductor integrated circuit driven by plural power supply voltages.
2. Description of the Related Art
In a conventional layout system for a semiconductor integrated circuit, layout processing (placement and routing processing) for a layout object circuit is performed using circuit connectivity information (net list) representing the connecting relation between circuit components in a multi-power supply layout object circuit and power supply information that associates a power supply voltage with a power supply terminal of a circuit component to be supplied with the power supply voltage. Specifically, in this layout system, signal terminals designated for interconnection by the net list are connected with each other and the power supply terminal and the power supply line of the power supply voltage associated with each other by the power supply information are connected with each other.
With respect to a layout design for a multi-power supply semiconductor integrated circuit, JP-A-2003-345853 discloses a verification method for a semiconductor integrated circuit that enables efficient detection of incorrect connection of circuit components in a layout object circuit without exceptions, and JP-A-2002-15018 discloses a design method for a semiconductor integrated circuit that enables easy designing of a layout for a multi-power supply semiconductor integrated circuit, in which, for example, the power supply lines for the multi-power supply can be automatically carried out.
In the conventional layout system for a semiconductor integrated circuit, since the corresponding relation between the signal terminal of the circuit component and the power supply voltage cannot be recognized from the net list and the power supply information, the power supply line to be connected to the signal terminal designated for input level fixation by the net list, or the position where a level-converting cell should be inserted and the type of the level-converting cell to be inserted cannot be automatically judged. Therefore, in the conventional layout system for a semiconductor integrated circuit, a person in charge of layout must manually carry out connection processing to connect the signal terminal for input level fixation and the power supply line, or insertion processing to insert the level-converting cell, while checking the circuit structure. As a result, incorrect connection due to the signal terminal for input level fixation or the level-converting cell tends to occur in layout verification such as LVS (Layout Verses Schematic) for verifying connection identity between the net list and layout data, and the number of repetitions of the layout processing and the layout verification increases. Thus, the design period for a semiconductor integrated circuit (layout design period) becomes longer. Moreover, JP-A-2003-345853 and JP-A-2002-15018 do not disclose any technique related to the connection processing to connect the signal terminal for input level fixation and the power supply line or the insertion processing to insert the level-converting cell.